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M34A02

same as the pattern applied on Chip Enable (E0,

E1, E2).

set to 1 for Read and 0 for Write operations. If a

match occurs on the Device Select code, the

corresponding device gives an acknowledgment

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Table 4. Operating Modes

Note: 1. X =

Mode

RW bit

Bytes

Initial Sequence

Current Address Read

1

X

1

START, Device Select, RW = 1

Random Address Read

0X

1

START, Device Select, RW = 0, Address

1

X

reSTART, Device Select, RW = 1

Sequential Read

1

X

≥ 1

Similar to Current or Random Address Read

Byte Write

0

1

START, Device Select, RW = 0

Page Write

0

≤ 16

START, Device Select, RW = 0

Figure 6. Write Mode Sequences with WC=1 (data write inhibited)

Byte Write

DEV SEL

BYTE ADDR

DATA IN

WC

Page Write

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

WC

DATA IN 3

AI02803C

Page Write

(cont'd)

WC (cont'd)

DATA IN N

ACK

ACK

NO ACK

R/W

ACK

ACK

NO ACK

NO ACK

R/W

NO ACK

NO ACK