SN74LS76A

http://onsemi.com

2

LOGIC DIAGRAM

Q

CLEAR (CD)

J

CLOCK (CP)

K

SET (SD)

Q

LOGIC SYMBOL

16

1

4

15

14

KQ

CP

JQ

SD

VCC = PIN 5

GND = PIN 13

12

6

9

11

10

KQ

CP

JQ

CD

7

2

3

8

CD

SD

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

VIK

Input Clamp Diode Voltage

–0.65

–1.5

V

VCC = MIN, IIN = –18 mA

VOH

Output HIGH Voltage

2.7

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOL

Output LOW Voltage

0.25

0.4

V

IOL = 4.0 mA

VCC = VCC MIN,

VIN VIL or VIH

VOL

Output LOW Voltage

0.35

0.5

V

IOL = 8.0 mA

VIN = VIL or VIH

per Truth Table

IIH

Input HIGH Current

J, K

Clear

Clock

20

60

80

µA

VCC = MAX, VIN = 2.7 V

IIH

Input HIGH Current

J, K

Clear

Clock

0.1

0.3

0.4

mA

VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

J, K

Clear, Clock

–0.4

–0.8

mA

VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

–20

–100

mA

VCC = MAX

ICC

Power Supply Current

6.0

mA

VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

30

45

MHz

tPLH

Clock Clear Set to Output

15

20

ns

VCC = 5.0 V

CL = 15 pF

tPLH

tPHL

Clock, Clear, Set to Output

15

20

ns

CL = 15 pF

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tW

Clock Pulse Width High

20

ns

tW

Clear Set Pulse Width

25

ns

VCC 50V

ts

Setup Time

20

ns

VCC = 5.0 V

th

Hold Time

0

ns