© 1995 Microchip Technology Inc.

DS11182C-page 5

85C72/82/92

4.0

SLAVE ADDRESS

The chip address inputs A0, A1 and A2 of each 85C72/

3-bit address. Up to eight 85C72/82/92s may be con-

nected to the bus. Chip selection is then accomplished

through software by setting the bits A0, A1 and A2 of

the transmitted slave address to the corresponding

hardwired logic levels of the selected 85C72/82/92.

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code (1010) for the 85C72/82/92, followed by the chip

address bits A0, A1 and A2. In the 85C92 the seventh

bit of that byte (BA) is used to select the upper block

(addresses 100 - 1FF) or the lower block (000 - FFF) of

the array.

The eighth bit of slave address determines if the master

device wants to read or write to the 85C72/82/92 (see

Figure 4-1).

The 85C72/82/92 monitors the bus for its correspond-

ing slave address all the time. It generates an acknowl-

edge bit if the slave address was true and it is not in a

programming mode.

FIGURE 4-1:

SLAVE ADDRESS

ALLOCATION

START

READ/WRITE

SLAVE ADDRESS

R/W

1

0

1

0

A2A1A0

A

5.0

BYTE PROGRAM MODE

In this mode, the master sends addresses and one

data byte to the 85C72/82/92.

Following the START condition, the device code (4-bit),

the slave address (3-bit), and the R/W bit, which is logic

LOW, are placed onto the bus by the master. This indi-

cates to the addressed 85C72/82/92 that a byte with a

word address will follow after it has generated an

acknowledge bit. Therefore, the next byte transmitted

by the master is the word address and will be written

into the address pointer of the 85C72/82/92.

After

receiving the acknowledge of the 85C72/82/92, the

master device transmits the data word to be written into

the addressed memory location.

The 85C72/82/92

acknowledges again and the master generates a

STOP condition. This initiates the internal program-

ming cycle of the 85C72/82/92 (see Figure 6-1).

6.0

PAGE PROGRAM MODE

To program the 85C72/82/92, the master sends

addresses and data to the 85C72/82/92 which is the

slave (see Figure 6-1). This is done by supplying a

START condition followed by the 4-bit device code, the

3-bit slave address, and the R/W bit which is defined as

a logic LOW for a write. This indicates to the addressed

slave that a word address will follow so the slave out-

puts the acknowledge pulse to the master during the

ninth clock pulse. When the word address is received

by the 85C72/82/92, it places it in the lower 8 bits of the

address pointer defining which memory location is to

be written. The 85C72/82/92 will generate an acknowl-

edge after every 8 bits received and store them con-

secutively in a 2-byte RAM until a stop condition is

detected which initiates the internal programming

cycle. If more than 2 bytes are transmitted by the mas-

ter, the 85C72/82/92 will terminate the write cycle. This

does not affect erase/write cycles of the EEPROM

array.

If the master generates a STOP condition after trans-

mitting the first data word (Point ‘P’ on Figure 6-1), byte

programming mode is entered.

The internal, completely self-timed PROGRAM cycle

starts after the STOP condition has been generated by

the master and all received (up to two) data bytes will

be written in a serial manner.

The PROGRAM cycle takes N milliseconds, whereby N

is the number of received data bytes (N max = 2).

FIGURE 6-1:

PROGRAM MODE (ERASE/WRITE)

START

STOP

A

DATA BYTE N

DATA BYTE 1

A

A

WORD

ADDRESS

A

0

R/W

P

ACKNOWLEDGES FROM SLAVE

SLAVE

ADDRESS