M35080-MN6T datasheet(6/18 Pages) STMICROELECTRONICS

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M35080

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(SRWD, BP0, BP1) become frozen at a constant

value. The updated value of these bits becomes

available when a new RDSR instruction is execut-

ed, after completion of the write cycle. On the oth-

er hand, the two read-only bits (WEL, WIP) are

dynamically updated during internal write cycles.

Using this facility, it is possible to poll the WIP bit

to detect the end of the internal write cycle.

The Comparator bit (INC) indicates if the new val-

ue written in the 16 first word is lower ‘1’ or higher

‘0’ than the previous stored value.

The UV bit indicates if the memory chip has been

erased.

Write Status Register (WRSR)

The format of the WRSR instruction is shown in

Figure 7. After the instruction and the eight bits of

the status register have been latched-in, the inter-

nal Write cycle is triggered by the rising edge of

the S line. This must occur after the falling edge of

the 16th clock pulse, and before the rising edge of

the 17th clock (as indicated in Figure 7), otherwise

the internal write sequence is not performed.

The WRSR instruction is used for the following:

to select the size of memory area that is to be

write-protected

to select between SPM (Software Protected

Mode) and HPM (Hardware Protected Mode).

The size of the write-protection area applies equal-

ly in SPM and HPM. The BP1 and BP0 bits of the

status register have the appropriate value (see Ta-

ble 7) written into them after the contents of the

protected area of the EEPROM have been written.

The initial delivery state of the BP1 and BP0 bits is

00, indicating a write-protection size of 0.

Figure 7. WRSR: Write Status Register Sequence

AI01797

3456789 10 11 12 13 14 15

HIGH IMPEDANCE

INSTRUCTION

STATUS REG.

765432

MSB

Figure 6. RDSR: Read Status Register Sequence

3456789 10 11 12 13 14 15

INSTRUCTION

AI02031

6543210

STATUS REG. OUT

HIGH IMPEDANCE

MSB

6543210

STATUS REG. OUT

MSB

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