M36DR432BD datasheet(9/52 Pages) STMICROELECTRONICS

부품명	M36DR432BD

상세설명	32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

PDF	52 Pages

Scroll/Zoom	100%

제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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M36DR432AD, M36DR432BD

the memory and reduces the power consumption

to the standby level. ES can also be used to con-

trol writing to the SRAM memory array, while WS

remains at VIL. It is not allowed to set EF at VIL and

ES at VIL at the same time.

SRAM Write Enable (WS). The Write Enable in-

put controls writing to the SRAM memory array.

WS is active Low.

SRAM Output Enable (GS). The Output Enable

gates the outputs through the data buffers during

a read operation of the SRAM chip. GS is active

Low.

SRAM Upper Byte Enable (UBS). Enables

the

upper bytes for SRAM (DQ8-DQ15). UBS is active

Low.

SRAM Lower Byte Enable (LBS). Enables the

lower bytes for SRAM (DQ0-DQ7). LBS is active

Low.

VDDS Supply Voltage (1.65V to 2.2V). VDDS is the

SRAM power supply for all operations.

Note: Each device in a system should have

VDDF and VPPF decoupled with a 0.1µF capaci-

tor close to the pin. See Figure 7, AC Measure-

ment Load Circuit. The PCB trace widths

should be sufficient to carry the required VPPF

program and erase currents.

M36DR432BD 데이터시트(PDF) 9 Page - STMicroelectronics