MSC8103 datasheet(8/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

1-4

Freescale Semiconductor

Signals/Connections

1.1 Power Signals

1.2 Clock Signals

Table 1-2.

Power and Ground Signal Inputs

Power Name

Description

VDD

Internal Logic Power

VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with

an extremely low impedance path to the VDD power rail.

VDDH

Input/Output Power

This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.

VCCSYN

System PLL Power

VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input

should be provided with an extremely low impedance path to the VCC power rail.

VCCSYN1

SC140 PLL Power

VCC dedicated for use with the SC140 core PLL. The voltage should be well-regulated and the input should be provided

with an extremely low impedance path to the VCC power rail.

GND

System Ground

An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground

connections, except GNDSYN and GNDSYN1. The user must provide adequate external decoupling capacitors.

GNDSYN

System PLL Ground

Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to

ground.

GNDSYN1

SC140 PLL Ground 1

Ground dedicated for SC140 core PLL use. The connection should be provided with an extremely low-impedance path

to ground.

Table 1-3.

Clock Signals

Signal Name

Type

Signal Description

CLKIN

Input

Clock In

Primary clock input to the MSC8103 PLL.

MODCK1

TC0

BNKSEL0

Input

Output

Clock Mode Input 1

Defines the operating mode of internal clock circuits.

Transfer Code 0

Supplies information that can be useful for debugging bus transactions initiated by the MSC8103.

Bank Select 0

Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode.

MODCK2

TC1

BNKSEL1

Input

Output

Clock Mode Input 2

Defines the operating mode of internal clock circuits.

Transfer Code 1

Supplies information that can be useful for debugging bus transactions initiated by the MSC8103.

Bank Select 1

Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode.

MODCK3

TC2

BNKSEL2

Input

Output

Clock Mode Input 3

Defines the operating mode of internal clock circuits.

Transfer Code 2

Supplies information that can be useful for debugging bus transactions initiated by the MSC8103.

Bank Select 2

Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode.

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