M48T86 datasheet(4/23 Pages) STMICROELECTRONICS

4 / 23 page

M48T86

4/23

DS (Data Strobe Input). The DS pin is also re-

ferred to as Read (RD). A falling edge transition on

the Data Strobe (DS) input enables the output dur-

ing a a read cycle. This is very similar to an Output

Enable (G) signal on other memory devices.

E (Chip Enable Input). The

Chip

Enable

must be asserted low for a bus cycle in the

M48T86 to be accessed. Bus cycles which take

place without asserting E will latch the addresses

present, but no data access will occur.

Figure 4. Block Diagram

AI01643

OSCILLATOR

BCD/BINARY

INCREMENT

/ 8

/ 64

PERIODIC INTERRUPT/SQUARE WAVE SELECTOR

SQUARE WAVE

OUTPUT

POWER

SWITCH

AND

WRITE

PROTECT

AD0-AD7

REGISTERS A,B,C,D

CLOCK CALENDAR,

AND ALARM RAM

STORAGE

REGISTERS

(114 BYTES)

CLOCK/

CALENDAR

UPDATE

BUS

INTERFACE

VCC

VBAT

VCC

POK

R/W

SQW

RST

IRQ

DOUBLE

BUFFERED

RCL

IRQ (Interrupt Request Output). The IRQ pin is

an open drain output that can be used as an inter-

rupt input to a processor. The IRQ output remains

low as long as the status bit causing the interrupt

is present and the corresponding interrupt-enable

bit is set. IRQ returns to a high impedance state

whenever Register C is read. The RST pin can

also be used to clear pending interrupts. Because

the IRQ bus is an open drain output, it requires an

external pull-up resistor to VCC.

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