M48Z30-100PM1 datasheet(7/12 Pages) STMICROELECTRONICS

7 / 12 page

Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

Note: W = High.

A write is terminated by the earlier rising edge of W

or E. The addresses must be held valid throughout

the cycle. E or W must return high for minimum of

tEHAX from E or tWHAX from W prior to the initiation

of another read or write cycle. Data-in must be valid

tDVWH prior to the end of write and remain valid for

tWHDX or tEHDX afterward. G should be kept high

during write cycles to avoid bus contention; al-

though, if the output bus has been activated by a

low on E and G, a low on W will disable the outputs

tWLQZ after W falls.

DATA RETENTION MODE

With valid VCC applied, the M48Z30/30Y operates

as a conventional BYTEWIDETM static RAM.

Should the supply voltage decay, the RAM will

automatically power-fail deselect, write protecting

itself tWP after VCC falls below VPFD. All outputs

become high impedance, and all inputs are treated

as ”don’t care.”

If power fail detection occurs during a valid access,

the memory cycle continues to completion. If the

memory cycle fails to terminate within the time tWP,

write protection takes place. When Vcc drops be-

low VSO, the control circuit switches power to the

internal energy source which preserves data.

The internal coin cell will maintain data in the

M48Z30/30Y after the initial application of VCC for

an accumulated period of at least 10 years when

VCC is less than VSO. As system power returns and

Vcc rises above VSO, the battery is disconnected,

and the power supply is switched to external Vcc.

Write protection continues for tER after VCC reaches

VPFD to allow for processor stabilization. After tER,

normal RAM operation can resume.

WRITE MODE (cont’d)

7/12

M48Z30, M48Z30Y

M48Z30-100PM1 데이터시트(PDF) 7 Page - STMicroelectronics