M50FW040N1 datasheet(6/41 Pages) STMICROELECTRONICS

6 / 41 page

M50FW040

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SUMMARY DESCRIPTION

The M50FW040 is a 4 Mbit (512Kb x8) non-vola-

tile memory that can be read, erased and repro-

grammed. These operations can be performed

using a single low voltage (3.0 to 3.6V) supply. For

fast erasing in production lines an optional 12V

power supply can be used to reduce the erasing

time.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Blocks can be

protected individually to prevent accidental Pro-

gram or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

Two different bus interfaces are supported by the

memory. The primary interface, the Firmware Hub

(or FWH) Interface, uses Intel’s proprietary FWH

protocol. This has been designed to remove the

need for the ISA bus in current PC Chipsets; the

M50FW040 acts as the PC BIOS on the Low Pin

Count bus for these PC Chipsets.

The secondary interface, the Address/Address

Multiplexed (or A/A Mux) Interface, is designed to

be compatible with current Flash Programmers for

production line programming prior to fitting to a PC

Motherboard.

The memory is offered in TSOP32 (8 x 14mm),

TSOP40 (10 x 20mm) and PLCC32 packages and

it is supplied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram (FWH Interface)

Table 1. Signal Names (FWH Interface)

AI03623

FWH4

FWH0-

FWH3

VCC

M50FW040

CLK

VSS

TBL

INIT

ID0-ID3

FGPI0-

FGPI4

VPP

FWH0-FWH3

Input/Output Communications

FWH4

Input Communication Frame

ID0-ID3

Identification Inputs

FGPI0-FGPI4

General Purpose Inputs

Interface Configuration

Interface Reset

INIT

CPU Reset

CLK

Clock

TBL

Top Block Lock

Write Protect

RFU

Reserved for Future Use. Leave

disconnected

VCC

Supply Voltage

VPP

Optional Supply Voltage for Fast

Erase Operations

VSS

Ground

Not Connected Internally

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