| 전자부품 데이터시트 검색엔진 |
|
DAC39RF10 데이터시트(PDF) 44 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DAC39RF10 데이터시트(HTML) 44 Page - Texas Instruments |
|
44 / 232 page ![]() 6.9 Switching Characteristics (continued) Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.242GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t FRCLK _PL FRCLK pulse width low 2 ns t FRDI_SU FRDI setup time 1 ns tFRDI _H FRDI hold time 1 ns t FRCS_SU FRCS setup time 1 ns t FRCS_H FRCS hold time 1 ns tFR_IAG Inter-access gap 1 ns (1) The delay depends on how long it takes the JESD link to start up and the mode dependent device latency. Add the link layer startup time and the mode dependent latency (TDAC_LAT) from the latency calculator spreadsheet. (2) Pulse durations less than this produce undefined behavior. (3) Pulse durations less than this may have no effect on the output. (4) 8b/10b encoding required for < 2Gbps DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 44 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |