| 전자부품 데이터시트 검색엔진 |
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REF6025IDGKT 데이터시트(PDF) 27 Page - Texas Instruments |
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REF6025IDGKT 데이터시트(HTML) 27 Page - Texas Instruments |
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27 / 35 page ![]() 9.3 Power Supply Recommendations The REF60xx family of references have extremely low dropout voltage. The dropout specifications can be found in Section 6.5. A minimum 0.1 µF decoupling capacitor must be connected between the VIN and GND_F pins of the REF60xx. A typical dropout voltage versus load is shown in Figure 9-8. 0 50 100 150 200 250 ±4 ±3 ±2 ±1 0 1 2 3 4 Load Current (mA) C017 -40ƒC 25ƒC 90ƒC 125ƒC Figure 9-8. Dropout Voltage vs Load Current 9.4 Layout 9.4.1 Layout Guidelines Figure 9-9 illustrates an example of a PCB layout for a data-acquisition system using the REF60xx. Some key considerations are: • Connect low-ESR, 0.1μF ceramic bypass capacitors between the VIN pin and ground. • Place the REF60xx output capacitor (CL) and the ADC as close to each other as possible. • Run two separate traces between VOUT_F, VOUT_S and the output capacitor, as shown in Figure 9-9. • Short the GND_F and GND_S pins with a solid plane, and extend this plane to connect to the output capacitor CL, as shown in Figure 9-9. • Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup. • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary. 9.4.2 Layout Example RSS CFILT RESR CIN REF60xx CL AGND VOUT REFP REFM ADC AGND VIN EN Copyright © 2016, Texas Instruments Incorporated Figure 9-9. Layout Example www.ti.com REF60 SBOS708C – MAY 2016 – REVISED APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: REF60 |
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