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DRA752ABC 데이터시트(PDF) 79 Page - Texas Instruments

부품명 DRA752ABC
상세설명  DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0
PDF  443 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

DRA752ABC 데이터시트(HTML) 79 Page - Texas Instruments

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Copyright © 2015–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744
79
DRA756, DRA755, DRA754, DRA752
DRA751, DRA750, DRA746, DRA745, DRA744
www.ti.com
SPRS950F – DECEMBER 2015 – REVISED MAY 2019
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE [10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
B26
xref_clk2
xref_clk2
0
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
mcasp2_axr10
1
IO
0
mcasp1_axr6
2
IO
0
mcasp3_ahclkx
3
O
mcasp7_ahclkx
4
O
atl_clk2
5
O
vout2_clk
6
O
vin4a_clk0
8
I
0
timer15
10
IO
gpio6_19
14
IO
Driver off
15
I
C23
xref_clk3
xref_clk3
0
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
mcasp2_axr11
1
IO
0
mcasp1_axr7
2
IO
0
mcasp4_ahclkx
3
O
mcasp8_ahclkx
4
O
atl_clk3
5
O
vout2_de
6
O
hdq0
7
IO
1
vin4a_de0
8
I
0
clkout3
9
O
timer16
10
IO
gpio6_20
14
IO
Driver off
15
I
(1) NA in this table stands for Not Applicable.
(2) For more information on recommended operating conditions, see Table 5-4, Recommended Operating Conditions.
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40
Ω. For more information on DS[1:0] register configuration, see the
Device TRM.
(5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
(6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
(7) This function will not be supported on some pin-compatibleroadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
(8) In PUx / PDy, x and y = 60 to 200 μA.
The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
(9) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (VDDSHV6 must be supplied with 1.8V). 3.3V mode is
not supported. This must be considered in the pin mux programming and VDDSHVx supply connections.



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