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DRA752ABC 데이터시트(PDF) 133 Page - Texas Instruments

부품명 DRA752ABC
상세설명  DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0
PDF  443 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

DRA752ABC 데이터시트(HTML) 133 Page - Texas Instruments

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DRA756, DRA755, DRA754, DRA752
DRA751, DRA750, DRA746, DRA745, DRA744
www.ti.com
SPRS950F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744
Terminal Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Table 4-27. Debug Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
tms
JTAG test port mode select. An external pullup resistor should be used on this
ball.
IO
F18
tdi
JTAG test data
I
D23
tdo
JTAG test port data
O
F19
tclk
JTAG test clock
I
E20
trstn
JTAG test reset
I
D20
rtck
JTAG return clock
O
E18
emu0(1)
Emulator pin 0
IO
G21
emu1(1)
Emulator pin 1
IO
D24
emu2
Emulator pin 2
O
F10
emu3
Emulator pin 3
O
D7
emu4
Emulator pin 4
O
A7
emu5
Emulator pin 5
O
E1 / G11
emu6
Emulator pin 6
O
G2 / E9
emu7
Emulator pin 7
O
H7 / F9
emu8
Emulator pin 8
O
G1 / F8
emu9
Emulator pin 9
O
G6 / E7
emu10
Emulator pin 10
O
F2 / D8
emu11
Emulator pin 11
O
F3 / A5
emu12
Emulator pin 12
O
D1 / C6
emu13
Emulator pin 13
O
E2 / C8
emu14
Emulator pin 14
O
D2 / C7
emu15
Emulator pin 15
O
F4 / A8
emu16
Emulator pin 16
O
C1 / C9
emu17
Emulator pin 17
O
E4 / A9
emu18
Emulator pin 18
O
F5 / B9
emu19
Emulator pin 19
O
E6 / A10
(1) EMU0 and EMU1 are multiplexed with GPIO. These pins will be sampled at reset release by the test and emulation logic. Therefore, if
they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can be controlled by logic driven
from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.
4.4.25 System and Miscellaneous
4.4.25.1 Sysboot
NOTE
For more information, see the Initialization (ROM Code) section of the device TRM.
Table 4-28. Sysboot Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
sysboot0
Boot Mode Configuration 0. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M6
sysboot1
Boot Mode Configuration 1. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M2
sysboot2
Boot Mode Configuration 2. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L5
sysboot3
Boot Mode Configuration 3. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M1



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