RH850SLASHF1KM datasheet(21/422 Pages) RENESAS

21 / 422 page

RH850/F1KH, RH850/F1KM

Section 1B Overview of RH850/F1KM-S4, RH850/F1KM-S2

R01DS0442EJ0100 Rev.1.00

Page 21 of 422

Sep 15, 2023

Note 1.

The trace RAM is only supported by products with 4 MB code flash memory.

Figure 1B.3

Internal Block Diagram (RH850/F1KM-S4 176-Pin Version)

P-Bus

Peripheral

Group 1

Peripheral

Group 2

Peripheral

Group 3

Peripheral

Group 4

Peripheral

Group 5

System interconnect

H-Bus

Global RAM

(192 KB (max.))

/Retention RAM

(64 KB)

DMA

(32 ch)

System control

LVI

CLMA

(4 ch)

LVI

MainOSC

LS IntOSC

HS IntOSC

PLL1

STBC

CVM

POC

LPS

Code flash

(4 MB (max.))

OSTM

(5 units)

CSIH

(4 ch)

CSIG

(4 ch)

RS-CANFD

(8 ch)

WDTA

(2 units)

TAUD

(1 unit)

TAUB

(2 unit)

TAUJ

(4 units)

RTCA

(1 unit)

ENCA

(1 unit)

Motor

control

PWM-Diag

(72 ch)

INTC2

DMA reg

ADCA0

RLIN3

(8 ch)

RLIN2

(10 ch)

RIIC

(2 ch)

(8 ch)

Flash

controller

DCRA

(4 ch)

Port

RSENT

(2 ch)

Data flash

(128 KB

(max.))

ICUMD

PLL0

FLXA

(2 ch)

Flash interface

SFMA

ADCA1

SubOSC

ETNB

MEMC

ETNB reg

Local RAM

(256 KB (max.))

Trace RAM*1

(32 KB)

Debug

INTC1

CPU1 (PE1)

SEG

CPU

core

MPU

FPU

IPG

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