M54HC195

M74HC195

October 1992

8 BIT PIPO SHIFT REGISTER

B1R

(Plastic Package)

ORDER CODES :

M54HC195F1R

M74HC195M1R

M74HC195B1R

M74HC195C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

DESCRIPTION

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

I

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS195

The M54/74HC195 is a high speed CMOS 4 BIT

PIPO SHIFT REGISTER fabricated in silicon gate

C

formance of LSTTL combined with true CMOS low

power consumption.

This shift register features parallel inputs, parallel

outputs, J-K serial inputs, a SHIFT/LOAD control

input, and a direct overriding CLEAR. This shift reg-

ister can operate in two modes : Parallel Load ; Shift

from QA towards QD.

Parallel loading is accomplished by applying the four

bits of data, and taking the SHIFT/LOAD control

input low. The data is loaded into the associated flip

flops and appears at the outputs after the positive

transition of the clock input. During parallel loading,

serial data flow is inhibited. Serial shifting occurs

synchronously when the SHIFT/LOAD control input

is high. Serial data for this mode is entered at the J-K

inputs. These inputs allow the first stage to perform

as a J-K or TOGGLE flip flop as shown in the truth-

table.

All inputs are equipped with protection circuits

against static discharge transient excess voltage.

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