TRUTH TABLE

INPUTS

OUTPUTS OF

ADDRESSED LATCH

EACH OTHER

OUTPUT

FUNCTION

CLEAR

ENABLE

H

L

D

Qi0

ADDRESSABLE LATCH

H

H

Qi0

Qi0

MEMORY

L

L

D

L

8 LINE DEMULTIPLEXER

L

H

L

L

CLEAR ALL BITS TO ’L’

D: The level at the data input

Qi0: The level before the indicated steady state input conditions were established, (i = 0, 1, .....,7).

LOGIC DIAGRAM

SELECT INPUTS

LATCH ADDRESSED

CB

A

LL

L

Q0

LL

H

Q1

LH

L

Q2

LH

H

Q3

HL

L

Q4

HL

H

Q5

HH

L

Q6

HH

H

Q7

M54/M74HC259

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