CS5460

DS279PP5

3

5. FUNCTIONAL DESCRIPTION ................................................................................... 26

5.1 Interrupt and Watchdog Timer......................................................................... 26

5.1.1 Interrupt.................................................................................................. 26

5.1.1.1 Clearing the Status Register ........................................................ 26

5.1.1.2 Typical use of the INT pin............................................................. 26

5.1.1.3 INT Active State ........................................................................... 26

5.1.1.4 Exceptions .................................................................................... 26

5.1.2 Watch Dog Timer ................................................................................... 26

5.2 Oscillator Characteristics................................................................................. 27

5.3 Analog Inputs .................................................................................................. 27

5.4 Voltage Reference........................................................................................... 28

5.5 Performing Calibrations ................................................................................... 28

5.5.1 System Calibration................................................................................. 28

5.5.2 Calibration Tips ...................................................................................... 29

5.6 Input Current Protection .................................................................................. 29

5.7 PCB Layout ..................................................................................................... 30

6. PIN DESCRIPTION..................................................................................................... 31

7. SPECIFICATION DEFINITIONS................................................................................. 32

8. PACKAGE DIMENSIONS .......................................................................................... 33

LIST OF FIGURES

Figure 1. SDI Write Timing (Not to Scale).......................................................................................8

Figure 2. SDO Read Timing (Not to Scale)..................................................................................... 8

Figure 3. Typical Connection Diagram (One-Phase 2-Wire)........................................................... 9

Figure 4. Typical Connection Diagram (One-Phase 3-Wire)......................................................... 10

Figure 5. Data Flow....................................................................................................................... 11

Figure 6. Voltage Input Filter Roll-off ............................................................................................ 12

Figure 7. Current Input Filter Roll-off............................................................................................. 12

Figure 8. Multi-Phase System ....................................................................................................... 13

Figure 9. CS5460 Register Diagram ............................................................................................. 14

Figure 10. Command and Data Word Timing ............................................................................... 19

Figure 11. Oscillator Connection................................................................................................... 27

Figure 12. System Calibration of Offset. ....................................................................................... 28

Figure 13. System Calibration of Gain. ......................................................................................... 28

LIST OF TABLES

Table 1. Specification with MCLK = 4.096 MHz, K = 1, and N = 4000.......................................... 10

Table 2. Internal Registers Default Value ..................................................................................... 20

Table 3. CPU Clock (and K) Restrictions ...................................................................................... 27