STM32WB09TE datasheet(7/73 Pages) STMICROELECTRONICS

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Functional overview

3.1

Arm® Cortex®–M0+ core with MPU

The STM3WB09xE contains an Arm® Cortex®-M0+ microprocessor core. The Arm® Cortex®-M0+ was developed

to provide a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-

power consumption, while delivering outstanding computational performance and an advanced response to

interrupts. The Arm® Cortex®-M0+ can run from 1 MHz up to 64 MHz.

The Arm® Cortex®-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-

stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small

but powerful instruction set and extensively optimized design, providing high-end processing hardware including a

single-cycle multiplier.

The interrupts are handled by the Arm® Cortex®-M0+ nested vector interrupt controller (NVIC). The NVIC controls

specific Arm® Cortex®-M0+ interrupts as well as the STM3WB09xE peripheral interrupts. With its embedded

Arm® core, the STM3WB09xE family is compatible with all ARM® tools and software.

3.2

System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:

•

Three masters:

–

CPU (Cortex®-M0+) core S-bus

–

DMA1

–

Radio system

•

Nine slaves:

–

Internal flash memory on CPU (Cortex®-M0+) S bus

–

Internal SRAM0 (16 Kbytes )

–

Internal SRAM1 (16 Kbytes )

–

Internal SRAM2 (16 Kbytes )

–

Internal SRAM3 (16 Kbytes )

–

APB0 peripherals (through an AHB to APB bridge)

–

APB1 peripherals (through an AHB to APB bridge)

–

AHB0 peripherals

–

AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even

when several high-speed peripherals work simultaneously.

STM32WB09xE

Functional overview

DS14210 - Rev 6

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