29F040 datasheet(12/31 Pages) STMICROELECTRONICS

12 / 31 page

Symbol

Alt

Parameter

Test Condition

M29F040

Unit

-120

-150

VCC = 5V

± 10% VCC = 5V ± 10%

Standard

Interface

Standard

Interface

Min

Max

Min

Max

tAVAV

tRC

Address Valid to Next Address Valid

E = VIL, G = VIL

120

150

tAVQV

tACC

Address Valid to Output Valid

E = VIL, G = VIL

120

150

tELQX

(1)

tLZ

Chip Enable Low to Output Transition

G = VIL

tELQV

(2)

tCE

Chip Enable Low to Output Valid

G = VIL

120

150

tGLQX

(1)

tOLZ

Output Enable Low to Output

Transition

E = VIL

tGLQV

(2)

tOE

Output Enable Low to Output Valid

E = VIL

tEHQX

tOH

Chip Enable High to Output

Transition

G = VIL

tEHQZ

(1)

tHZ

Chip Enable High to Output Hi-Z

G = VIL

tGHQX

tOH

Output Enable High to Output

Transition

E = VIL

tGHQZ

(1)

tDF

Output Enable High to Output Hi-Z

E = VIL

tAXQX

tOH

Address Transition to Output

Transition

E = VIL, G = VIL

Notes: 1. Sampled only, not 100% tested.

2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.

Table 12B. Read AC Characteristics

(TA = 0 to 70

°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Program (PG) instruction. The memory can be

programmed Byte-by-Byte. This instruction uses

four write cycles. The Program command A0h is

written on the third cycle after two coded cycles. A

fourth write operation latches the Address on the

falling edge of W or E and the Data to be written

on its rising edge and starts the P/E.C. During the

execution of the program by the P/E.C., the mem-

ory will not accept any instruction. Read operations

output the status bits after the programming has

started. The status bits DQ5, DQ6 and DQ7 allow

a check of the status of the programming operation.

Memory programming is made only by writing ’0’ in

place of ’1’ in a Byte.

Erase Suspend (ES) instruction.

The Block

Erase operation may be suspended by this instruc-

tion which consists of writing the command 0B0h

without any specific address code. No coded cycles

are required. It allows reading of data from another

block while erase is in progress. Erase suspend is

accepted only during the Block Erase instruction

execution and defaults to read array mode. Writing

this command during Erase timeout will, in addition

to suspending the erase, terminate the timeout.

The Toggle Bit DQ6 stops toggling when the P/E.C.

is suspended. Toggle Bit status must be monitored

at an address out of the block being erased. Toggle

Bit will stop toggling between 0.1

µs and 15µs after

the Erase Suspend (ES) command has been writ-

ten.

The M29F040 will then automatically set to Read

Memory Array mode. When erase is suspended,

Read from blocks being erased will output invalid

data, Read from block not being erased is valid.

During the suspension the memory will respond

only to Erase Resume (ER) and Reset (RST) in-

structions. RST command will definitively abort

erasure and result in the invalid data in the blocks

being erased.

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