M58LW032A datasheet(40/61 Pages) STMICROELECTRONICS

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M58LW032A

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Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output

Note: 1. Valid Data Ready = Valid Low during valid clock edge (M8 = 0)

2. V= Valid output, NV= Not Valid output.

3. R is an open drain output with an internal pull up resistor of 1M

Ω. Depending on the Valid Data Ready pin capacitance load an

external pull up resistor must be chosen according to the system clock period.

Table 20. Synchronous Burst Read AC Characteristics

Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.

Symbol

Parameter

Test Condition

M58LW032A

Unit

110

tAVKH

Address Valid to Active Clock Edge

E = VIL

Min

tAVLH

Address Valid to Latch Enable High

E = VIL

Min

tELKH

Chip Enable Low to Active Clock Edge

E = VIL

Min

tELLH

Chip Enable Low to Latch Enable High

E = VIL

Min

tGLKH

Output Enable Low to Valid Clock Edge

E = VIL, L = VIH

Min

tKHAX

Valid Clock Edge to Address Transition

E = VIL

Min

tKHLL

Valid Clock Edge to Latch Enable Low

E = VIL

Min

tKHLH

Valid Clock Edge to Latch Enable High

E = VIL

Min

tKHQX

Valid Clock Edge to Output Transition

E = VIL, G = VIL, L = VIH

Min

tLLKH

Latch Enable Low to Valid Clock Edge

E = VIL

Min

tLLLH

Latch Enable Low to Latch Enable High

E = VIL

Min

tKHQV

Valid Clock Edge to Output Valid

E = VIL, G = VIL, L = VIH

Max

tQVKH

Output Valid to Active Clock Edge

E = VIL, G = VIL, L = VIH

Min

tRLKH

Valid Data Ready Low to Valid Clock Edge

E = VIL, G = VIL, L = VIH

Min

AI05510

Output (2)

tRLKH

(3)

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