M58LW032 datasheet(12/61 Pages) STMICROELECTRONICS

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M58LW032A

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one cycle before. Valid Data Ready Low, VOL, in-

dicates that the data is not, or will not be valid. Val-

id Data Ready in a high-impedance state indicates

that valid data is or will be available.

Unless Synchronous Burst Read has been select-

ed, Valid Data Ready is high-impedance. It may be

tied to other components with the same Valid Data

Ready signal to create a unique System Ready

signal.

The Valid Data Ready, R, output has an internal

pull-up resistor of approximately 1 M

Ω powered

from VDDQ, designers should use an external pull-

up resistor of the correct value to meet the external

timing requirements for Valid Data Ready rising.

Refer to Figure 19.

Ready/Busy (RB). The Ready/Busy output, RB,

is an open-drain output that can be used to identify

if the Program/Erase Controller is currently active.

When Ready/Busy is high impedance, the memo-

ry is ready for any Read, Program or Erase opera-

tion. Ready/Busy is Low, VOL, during Program and

Erase operations. When the device is busy it will

not accept any additional Program or Erase com-

mands except Program/Erase Suspend. When the

Program/Erase Controller is idle, or suspended,

Ready Busy can float High through a pull-up resis-

tor.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Ready/Busy is not Low during a reset unless the

reset was applied when the Program/Erase Con-

troller was active; Ready/Busy can rise before Re-

set/Power-Down rises.

Program/Erase Enable (VPP). The

Program/

Erase Enable input, VPP, is used to protect all

blocks, preventing Program and Erase operations

from affecting their data.

Program/Erase Enable must be kept High during

all Program/Erase Controller operations, other-

wise the operations is not guaranteed to succeed

and data may become corrupt.

VDD Supply Voltage. VDD provides the power

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

VDDQ Supply Voltage. VDDQ provides the power

supply to the I/O pins and enables all Outputs to

be powered independently from VDD. VDDQ can be

tied to VDD or can use a separate supply.

It is recommended to power-up and power-down

VDD and VDDQ together to avoid any condition that

would result in data corruption.

VSS Ground. Ground, VSS, is the reference for

the core power supply. It must be connected to the

system ground.

VSSQ Ground. VSSQ ground is the reference for

the input/output circuitry driven by VDDQ. VSSQ

must be connected to VSS.

Note: Each device in a system should have

VDD and VDDQ decoupled with a 0.1µF ceramic

capacitor close to the pin (high frequency, in-

herently low inductance capacitors should be

as close as possible to the package). See Fig-

ure 10, AC Measurement Load Circuit.

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