M59DR032A datasheet(19/38 Pages) STMICROELECTRONICS

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M59DR032A, M59DR032B

POWER SUPPLY

Power Down

The memory provides Reset/Power Down control

input RP. The Power Down function can be acti-

vated only if the relevant Configuration Register bit

is set to ’1’. In this case, when the RP signal is

pulled at VSS the supply current drops to typically

ICC2 (see Table 22), the memory is deselected and

the outputs are in high impedance.If RP is pulled

to VSS during a Program or Erase operation, this

operation is aborted in tPLQ7V and the memory

content is no longer valid (see Reset/Power Down

input description).

Power Up

The memory Command Interface is reset on Pow-

er Up to Read Array. Either E or W must be tied to

VIH during Power Up to allow maximum security

and the possibility to write a command on the first

rising edge of W.

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

have the VDD rails decoupled with a 0.1µF capac-

itor close to the VDD, VDDQ and VSS pins. The PCB

trace widths should be sufficient to carry the re-

quired VDD program and erase currents.

Table 21. Program, Erase Times and Program, Erase Endurance Cycles

(TA = 0 to 70°C; VDD = VDDQ = 1.65V to 2.2V, VPP = VDD unless otherwise specified)

Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or

erase should perform significantly better.

2. Excludes the time needed to execute the sequence for program instruction.

Parameter

M59DR032

Unit

Min

Max (1)

Typ

Typical after

100k W/E Cycles

Parameter Block (4 KWord) Erase (Preprogrammed)

2.5

0.15

0.4

sec

Main Block (32 KWord) Erase (Preprogrammed)

sec

Bank Erase (Preprogrammed, Bank A)

sec

Bank Erase (Preprogrammed, Bank B)

sec

Chip Program (2)

sec

Chip Program (DPG, VPP = 12V)

(2)

sec

Word Program

200

µs

Program/Erase Cycles (per Block)

100,000

cycles

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