M616Z08 datasheet(8/14 Pages) STMICROELECTRONICS

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M616Z08

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WRITE Mode

The M616Z08 is in the WRITE mode whenever the

WE0 (low memory addresses) or WE1 (high mem-

ory addresses) and CE pins are low (see Table 8,

page 10). Either the Chip Enable input (CE)orthe

WRITE Enable input (WE0 or WE1) must be de-

asserted during Address transitions for subse-

quent WRITE cycles. WRITE begins with the con-

currence of Chip Enable being active with WE0 or

WE1 low. Therefore, address setup time is refer-

enced to WRITE Enable and Chip Enable as tAVWL

and tAVEH respectively, and is determined by the

latter occurring edge.

The WRITE cycle can be terminated by the earlier

rising edge of CE,or WE0/WE1.

if the Output is enabled (CE = Low and OE =Low),

then WE0 or WE1 will return the outputs to high

impedance within tWLQZ of its falling edge. Care

must be taken to avoid bus contention in this type

of operation. Data input must be valid for tDVWH

before the rising edge of WRITE Enable, or for tD-

VEH before the rising edge of CE, whichever oc-

curs first, and remain valid for tWHDX or tEHDX.

Note: When using MCP555 with TO Pin high, re-

laxed WRITE timing (CSNT = 1inthe chip select

configuration register) should be selected.

Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms

Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms

Note: 1. Output Enable (OE) = High.

2. If CE goes High with WE0 or WE1 high, the output remains in a high-impedance state.

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A12

WE (0,1)

DQ0-DQ15

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI04211

tAVAV

tEHAX

tDVEH

DATA INPUT

A0-A12

WE (0,1)

DQ0-DQ15

VALID

tAVEH

tAVEL

tAVWL

tEHDX

tELEH

AI05639

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