M68AF127B datasheet(16/23 Pages) STMICROELECTRONICS

부품명	M68AF127B

상세설명	1Mbit 128K x8, 5V Asynchronous SRAM

PDF	23 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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M68AF127B

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Figure 14. E1 Controlled, Low VCC Data Retention AC Waveforms

Figure 15. E2 Controlled, Low VCC Data Retention AC Waveforms

Table 9. Low VCC Data Retention Characteristics

Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤0.2V.

2. Tested initially and after any design or process that may affect these parameters.

tAVAV is Read cycle time.

3. No input may exceed VCC +0.2V.

AI07204

DATA RETENTION MODE

5.5V

tCDR

VCC

4.5V

VDR > 2.0V

≥ VDR – 0.2V

AI07205B

DATA RETENTION MODE

5.5V

tCDR

VCC

4.5V

VDR > 2.0V

≤ 0.2V

Symbol

Parameter

Test Condition

Min

Max

Unit

ICCDR

(1)

Supply Current (Data Retention)

VCC = 2.0V, E1 ≥ VCC –0.2V or

≤0.2V, f = 0

4.5

µA

tCDR

(1,2)

Chip Deselected to Data Retention Time

(2)

Operation Recovery Time

tAVAV

VDR

(1)

Supply Voltage (Data Retention)

≥ VCC –0.2V or E2 ≤0.2V, f = 0

2.0

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