M68AR512DZB datasheet(3/19 Pages) STMICROELECTRONICS

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M68AR512D

SUMMARY DESCRIPTION

The M68AR512D is an 8 Mbit (8,388,608 bit)

CMOS SRAM, organized as 524,288 words by 16

bits. The device features fully static operation re-

quiring no external clocks or timing strobes, with

equal address access and cycle times. It requires

a single 1.8V (±150mV) supply. This device has a

Chip Select pin (E2) for easy memory expansion;

when it is active (E2 high) the device has an auto-

matic power-down feature, reducing the power

consumption by over 99%.

The

M68AR512D

available

TFBGA48

(6x7mm and 8x10mm, 6x8 active ball array, 0.75

mm ball pitch) package. See the Ordering Informa-

tion Scheme (Table 12) for details.

Figure 2. Logic Diagram

Table 1. Signal Names

AI03953C

A0-A18

DQ0-DQ15

VCC

M68AR512D

VSS

A0-A18

Address Inputs

DQ0-DQ15

Data Input/Output

E1, E2

Chip Enable

Output Enable

Write Enable

Upper Byte Enable Input

Lower Byte Enable Input

VCC

Supply Voltage

VSS

Ground

Not Connected

Don’t Use as Internally Connected

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