RTL8181
CONFIDENTIAL
v1.0
21
The read access timing of flash memory:
A[20..0]
F_CE0#
WE#
OE#
D[n..0]
8. Ethernet Controller
There are two 10/100M Ethernet MAC embedded in RTL8181. The Ethernet device has bus master capability, which will
move packets between SDRAM and Ethernet controller through DMA mechanism. Thus, it could offload the CPU loading and
get better performance. Besides, it also supports full-duplex operation, making possible 200Mbps bandwidth at no additional
cost.
Ethernet 0 Register Set (LAN PORT)
Virtual Address Size (byte)
Name
Description
Access
0xBD20_0000
4
ETH0_CNR1
Control register 1
R/W
0xBD20_0004
6
ETH0_ID
NIC ID
R/W
0xBD20_000C
8
ETH0_MAR
Multicast register
R/W
0xBD20_00 14
4
ETH0_TSAD
Transmit Starting Logic Address of
Descriptor
R/W
0xBD20_00 18
4
ETH0_RSAD
Receive Starting Logic Address of
Descriptor
R/W
0xBD20_00 20
2
ETH0_IMR
Ethernet0 Interrupt Mask Register
R/W
0xBD20_00 24
2
ETH0_ISR
Ethernet0 Interrupt Status Register
R/W
0xBD20_00 28
4
ETH0_TMF0
Type match filter 0 register
R/W
0xBD20_00 2C
4
ETH0_TMF1
Type match filter 1 register
R/W
0xBD20_00 30
4
ETH0_TMF2
Type match filter 2 register
R/W
0xBD20_0034
4
ETH0_TMF3
Type match filter 3 register
R/W
0xBD20_00 38
4
ETH0_MII
MII access register
R/W
0xBD20_00 3C
4
ETH0_CNR2
NIC control register 2
R/W
0xBD20_0040
16
ETH0_UAR
Unicast address filter register
R/W
0xBD20_0080
3
ETH0_MPC
Indicates the number of packets
discarded due to rx FIFO overflow.
It is a 24-bit counter. It is cleared to
zero by read command.
R
0xBD20_0084
2
ETH0_TXCOL Transmit collision counter. This
16-bit counter increments by 1 for
every collision event. It rolls over
when becomes full. It is cleared to
zero by read command.
R
0xBD20_0088
2
ETH0_RXER
Receive error count. This 16-bit
counter increments by 1 for each
valid packet received . It is cleared
to zero by read command.
R
Ethernet 1 Register Set (WAN PORT)
Virtual Address Size (byte)
Name
Description
Access
0xBD30_0000
4
ETH1_CNR1
Control register 1
R/W
0xBD30_0004
6
ETH1_ID
NIC ID
R/W
0xBD30_000C
8
ETH1_MAR
Multicast register
R/W
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