M68AW127B datasheet(14/20 Pages) STMICROELECTRONICS

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M68AW127B

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Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms

Note: 1. For 100ns speed class VDR ≥ 2.0V.

Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms

Note: 1. For 100ns speed class VDR ≥ 2.0V.

Table 9. Low VCC Data Retention Characteristics

Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V.

2. Tested initially and after any design or process that may affect these parameters.

tAVAV is Read cycle time.

3. No input may exceed VCC +0.2V.

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

ICCDR

(1)

Supply Current

(Data Retention)

VCC = 1.5V, E1 ≥ VCC –0.2V or

≤ 0.2V, f = 0

4.5

µA

100

µA

tCDR

(1,2)

Chip Deselected to Data

Retention Time

0ns

(2)

Operation Recovery Time

tAVAV

100

VDR

(1)

Supply Voltage

(Data Retention)

≥ VCC –0.2V or

≤ 0.2V, f = 0

1.5

100

2.0

AI05980

DATA RETENTION MODE

3.6V

tCDR

VCC

2.7V

VDR > 1.5V

(1)

≥ VDR – 0.2V

AI05957B

DATA RETENTION MODE

3.6V

VCC

2.7V

VDR > 1.5V

(1)

≤ 0.2V

tCDR

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