M7020R datasheet(117/150 Pages) STMICROELECTRONICS

117 / 150 page

117/150

M7020R

Figure 86. Multi-Width Configurations Example

LRAM AND LDEV DESCRIPTION

When search engines are cascaded using multiple

M7020Rs, the SADR, CE_L, and WE_L (3-state

signals) are all tied together. In order to eliminate

external pull-up and pull-downs, one device in a

bank is designated as the default driver. For non-

SEARCH or non-LEARN cycles (see LEARN

COMMAND in the section below) or search cycles

with a global miss, the SADR, CE_L, and WE_L

signals are driven by the device with the LRAM Bit

set.

Note: It is important that only one device in a bank

of search engines that are cascaded have this bit

set. Failure to do so will cause contention on

SADR, CE_L, WE_L, and can potentially cause

damage to the device(s).

Similarly, when search engines using multiple

M7020Rs are cascaded, SSF and SSV (also 3-

state signals) are tied together. In order to elimi-

nate external pull-up and pull-downs, one device

in a bank is designated as the default driver. For

non-SEARCH cycles or SEARCH cycles with a

global miss the SSF and SSV signals are driven by

the device with the LDEV Bit set.

Note: It is important that only one device in a bank

of search engines that are cascaded together

have this bit set. Failure to do so will cause conten-

tion on SSV and SSF and can potentially cause

damage to the device(s).

16 K

4 K

2 K

136

272

CFG = 10 01 00 00

AI06314

M7020R 데이터시트(PDF) 117 Page - STMicroelectronics