TDA7541W datasheet(38/76 Pages) STMICROELECTRONICS

38 / 76 page

Functional description

TDA7541

38/76

4.4

PLL and IF counter section

4.4.1

PLL frequency synthesizer block

This part contains a frequency synthesizer and a loop filter for radio tuning system. Only one

VCO is required to build a complete PLL system for FM world tuning and AM up conversion.

VCO and dividers

The varactor tuned LC oscillator together with the dividers provides the local oscillator signal

for both AM and FM front-end mixers. The VCO has an operating frequency of

approximately 160MHz to 260MHz. In FM mode the VCO frequency is divided (VCOD) by 1,

2 or 3. These dividers generate in-phase and quadrature-phase output signals using in FM

mixer for image rejection.

In AM mode the divided VCO frequency is additional predivided (AMD) by 4, 6, 8 or 10

dependent on selected AM band.

PLL frequency generation for phase comparison

The VCO divided signals applies a two modulus counter (32/33), which is controlled by a 5-

bit A-divider. The 5-bit register (PC0 to PC4) controls this divider. In parallel the output of the

swallow counter is connected to an 11-bit B-divider. The 11-bit PC register (PC5 to PC15)

controls this divider. Dividing range behind VCO divider:

Important: For correct operation: A

≤ 32; B ≥ A

Crystal oscillator

The crystal oscillator provides 10.25MHz signal for conversion from IF1 to IF2 as well as

switching signals for ISS- and quality detection filter. Furthermore reference dividers

generate from adjustable crystal frequency (XTAL) reference frequencies for the tuning PLL,

IF counter and FM demodulator.

The various reference frequencies fREF of PLL (RC) can be chosen by IIC-bus.

Three state phase comparator

The phase comparator generates a phase error signal according to phase difference

between fSYN and fREF. This phase error signal drives the charge pump current generator.

Charge pump current generator

This system generator signed pulses of current. The phase error signal decides the duration

and polarity of those pulses. The current absolute values are programmable by register ICP.

In lock detector

After reaching a phase difference about lower than 40nsec the inlock detector is

automatically switching the charge-pump in low current mode (LDENA).

VCOdiv

•

[] ƒ

REF

•

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