AS7343 datasheet(37/58 Pages) AMSOSRAM

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AS7343

Datasheet

• PUBLIC

DS001046

• v6-00 • 2023-Jun-07

│ 36

SP_TH_H_LSB Register (Address 0x86)

Figure 41:

SP_TH_H_LSB Register

Addr: 0x86

SP_TH_H_LSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_H_LSB

0x00

Spectral High Threshold LSB

This register provides the low byte of the high

interrupt threshold (CH0).

SP_TH_H_MSB Register (Address 0x87)

Figure 42:

SP_TH_H_MSB Register

Addr: 0x87

SP_TH_H_MSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_H_MSB

0x00

Spectral High Threshold MSB

This register provides the high byte of the high

interrupt threshold (CH0).

Both SP_TH_H registers are combined to a 16-bit

threshold. If the value captured by channel 0 is

above the high threshold and the APERS value is

reached, the bit SP_IEN is set and an interrupt is

generated.

CFG12 Register (Address 0x66)

Figure 43:

CFG12 Register

Addr: 0x66

CFG12

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

2:0

SP_TH_CH

Spectral Threshold Channel.

Sets the channel used for interrupts and persistence,

if enabled, to determine device status and gain

settings.

VALUE

CHANNEL

CH0

CH1

CH2

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