CMV4000 datasheet(39/92 Pages) AMSOSRAM

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CMV4000

Functional description

Datasheet

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Figure 26: 10-bit pixel data on an LVDS channel

The time ‘T1’ in Figure 26 is 1/10th of the period of the CLK_IN input clock. If a frequency of

48MHz is used for CLK_IN (max in 10-bit mode), this results in a 240 MHz OUTCLK

frequency.

Figure 27: 12-bit pixel data on an LVDS channel

The time ‘T2’ in Figure 27 is 1/12th of the period of the CLK_IN input clock. If a frequency of

40MHz is used for CLK_IN (max in 12-bit mode), this results in a 240 MHz OUTCLK

frequency.

7.3.3

Read-out timing

The read-out of image data is grouped in bursts of 128 pixels per channel. Each pixel is either

10 or 12 bits of data (see Chapter 7.3.2). One complete pixel period equals one period of the

master clock input. For details on pixel remapping and pixel vs. channel location please see

chapter 7.3.4 of this document. An overhead time exists between two bursts of 128 pixels. This

overhead time has the same length of one pixel read-out (i.e. the length of 10 or 12 bits at the

selected data rate or one master clock period). For details on how to program the sequencer

for different output modes, see chapter 7.5.1.

OUTCLK_P

OUTX_P

D10

D11

D10

D11

OUTCLK_P

OUTX_P

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