CMV50000 datasheet(64/137 Pages) AMSOSRAM

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CMV50000

Functional Description

Datasheet

• PUBLIC

DS000522

• v4-00 • 2023-Aug-03

136

│ 63

Figure 69:

Set PLL Sequence

Bank

Address

Value

106

110

114

107

pll1_pre_div (see calculation below)

109

pll1_clkout_sel (see calculation below)

108

pll1_ndiv (see calculation below)

112

pll2_ndiv (see calculation below)

114

106

110

The parameter pll1_pre_div depends only on the frequency of the sensor input clock CLK_IN

(between 6 MHz and 96 MHz).

Figure 70:

CLK_IN Divider Selection

CLK_IN

pll1_pre_div

6 MHz

– 12 MHz

12 MHz

– 24 MHz

24 MHz

– 48 MHz

48 MHz

– 96 MHz

The parameter pll1_clkout_sel depends only on the targeted output data rate.

Figure 71:

Data Rate Selection

Target Output Data Rate

pll1_clkout_sel

460

– 830 Mbit/s

230

– 460 Mbit/s

120

– 230 Mbit/s

The parameter pll1_ndiv depends on the frequency of the sensor input clock CLK_IN as well as the

desired output data rate.

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