ADSP-21990 datasheet(19/50 Pages) AD

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ADSP-21990

Rev. A

Page 19 of 50

August 2007

SPECIFICATIONS

Specifications subject to change without notice.

RECOMMENDED OPERATING CONDITIONS—ADSP-21990BBC

RECOMMENDED OPERATING CONDITIONS—ADSP-21990BST

Parameter

Conditions

Min

Typ

Max

Unit

VDDINT

Internal (Core) Supply Voltage

2.375

2.5

2.625

VDDEXT

External (I/O) Supply Voltage

3.135

3.3

3.465

AVDD

Analog Supply Voltage

2.375

2.5

2.625

CCLK

DSP Instruction Rate, Core Clock

150

MHz

HCLK1, 2

1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK

2, up to a maximum of a 75 MHz HCLK for the ADSP-21990BBC.

Peripheral Clock Rate

MHz

CLKIN3

3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

Input Clock Frequency

150

MHz

TJUNC

4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

Silicon Junction Temperature

140ºC

TAMB

Ambient Operating Temperature

–40ºC

+85ºC

Parameter

Conditions

Min

Typ

Max

Unit

VDDINT

Internal (Core) Supply Voltage

2.375

2.5

2.625

VDDEXT

External (I/O) Supply Voltage

3.135

3.3

3.465

AVDD

Analog Supply Voltage

2.375

2.5

2.625

CCLK

DSP Instruction Rate, Core Clock

160

MHz

HCLK

1, 2

1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK/2, up to a maximum of an 80 MHz HCLK for the ADSP-21990BST.

Peripheral Clock Rate

MHz

CLKIN

3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

Input Clock Frequency

160

MHz

TJUNC

4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

Silicon Junction Temperature

140ºC

TAMB

Ambient Operating Temperature

–40ºC

+85ºC

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