ADSP-21990BBC datasheet(25/50 Pages) AD

25 / 50 page

ADSP-21990

Rev. A

Page 25 of 50

August 2007

Clock In and Clock Out Cycle Timing

Table 6 and Figure 7 describe clock and reset operations. Com-

binations of CLKIN and clock multipliers must not select

core/peripheral clocks in excess of 160 MHz/80 MHz for the

ADSP-21990BST and 150 MHz/75 MHz for the

ADSP-21990BBC, when the peripheral clock rate is one-half the

core clock rate. If the peripheral clock rate is equal to the core

clock rate, the maximum peripheral clock rate is 80 MHz for the

ADSP-21990BST and 75 MHz for the ADSP-21990BBC. The

peripheral clock is supplied to the CLKOUT pins.

When changing from bypass mode to PLL mode, allow 512

HCLK cycles for the PLL to stabilize.

Table 6. Clock In and Clock Out Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements

tCK

CLKIN Period1, 2

200

tCKL

CLKIN Low Pulse

4.5

tCKH

CLKIN High Pulse

4.5

tWRST

RESET Asserted Pulse Width Low

200tCLKOUT

tMSS

MSELx/BYPASS Stable Before RESET Deasserted Setup

μs

tMSH

MSELx/BYPASS Stable After RESET Deasserted Hold

1000

tMSD

MSELx/BYPASS Stable After RESET Asserted

200

tPFD

Flag Output Disable Time After RESET Asserted

Switching Characteristics

tCKOD

CLKOUT Delay from CLKIN

5.8

tCKO

CLKOUT Period3

12.5

1 In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), tCK = tCCLK.

2 In bypass mode, tCK = tCCLK.

3 CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.

Figure 7. Clock In and Clock Out Cycle Timing

tCKOD

CLKOUT

MSEL6–0

BYPASS

RESET

CLKIN

tWRST

tCKH

tCK

tCKL

tMSH

tCKO

tPFD

tMSD

tMSS

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