MK50H28 datasheet(18/64 Pages) STMICROELECTRONICS

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CSR

DATA

4.1.1.2 Register Data Port (RDP)

BIT

NAME

DESCRIPTION

15:00

CSR DATA

Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from

RDP reads the data from the CSR selected in RAP.

4.1.2 Control and Status Register Definition

4.1.2.1 Control and Status Register 0 (CSR0)

RAP<3:1> = 0

BIT

NAME

DESCRIPTION

PTDMD

Transmit Demand for Priority DLCIs. Setting this bit to 1 causes the MK50H28 to jump to

Priority DLCI Block (PDB). This bit is cleared by the MK50H28 after servicing all active

entries in the PDB. (Note: See section 4.2.9 for more details.)

STOP

STOP, when set, indicates that MK50H28 is operating in the STOPPED Phase of

operation. All external activity is disabled and internal logic is reset. MK50H28 remains

inactive except for primitive processing until a START primitive is issued. STOP IS READ

ONLY and set by Bus RESET or a STOP primitive. Writing to this bit has no effect.

DTX

Disable Transmitter. Prevents the MK50H28 from further access to the Transmitter

Descriptor Rings. No transmissions are attempted after finishing transmission of any

frame in transmission at the time of DTX being set. Even LMI frames normally generated

automatically will not be transmitted if DTX=1. TXON acknowledges changes to DTX,

see below. DTX is READ/WRITE.

DRX

Disable the Receiver prevents the MK50H28 from further access to the Receiver

Descriptor Rings. No received frames are accepted after finishing reception of any frame

in reception at the time of DRX being set. Setting DRX will put the MK50H28 in the

LOCAL BUSY Phase. RXON acknowledges changes to DRX, see description of RXON.

DRX is READ/WRITE.

MK50H28

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