MK68901 datasheet(15/33 Pages) STMICROELECTRONICS

15 / 33 page

Figure 18 : Receiver Status Register (RSR).

BF :

Buffer Full. This bit is set when the inco-

ming word is transferred to the receive

buffer. The bit is cleared when the re-

ceive buffer is read by reading the UDR.

This bit of the RSR is read only.

OE :

Overrun Error. This flag is set if the inco-

ming word is completely received and

due to be tranferred to the receive buf-fer,

but the last word in the receive buf-fer has

not yet been read. When this condition

occurs, the word in the receive buffer is

not overwritten by the new word. Note

that the status flags always reflect the

status of the data word currently in the re-

ceive buffer. As such, the OE flag is not

actually set until the good word currently

in the buffer has been read. The interrupt

associated with this error will also not be

generated unti the old word in the receive

buffer has been read.

OE flag is cleared by reading the receiver

status register, and new data words can-

not be shifted to the receive buffer until

this is done.

PE :

Parity Error. This flag is set if the word re-

ceived has a parity error. The flag is set

when the received word is tranferred

from the shift register to the receive buf-

fer if the error condition exists. The flag is

cleared when the next word which does

not have a parity error is tranferred to the

receive buffer.

FE :

Frame Error. This flag only applies to the

asynchronous format. A frame error is

defined as a non-zero data word which is

not followed by a stop bit. Like the PE

flag, the FE flag is set or cleared when a

word is transferred to the receive buffer.

F/S :

Found/Search. This combination control

bit and flag bit is only used with the syn-

chronous format. It can be set or cleared

by writing to this bit of the RSR. When this

bit is cleared, the receiver is placed in the

search mode. In this mode, a bit by bit

comparison of the incoming data to the

character in the Sync Character Register

(SCR) is made. The word length counter

is disabled. When a match is found, this

bit will be set automatically, and the word

length counter will start as sync has not

been achieved. An interrupt will be gene-

rated on the receive error channel when

the match occurs. The word just shifted

in will, or necessity, be equal to the sync

character, and it will not be transferred to

the receive buffer.

B :

Break. This flag is used only when the a-

synchronous format is selected. This flag

will be set when an all zero data word, fol-

lowed by no stop bit, is received. The flag

will stay set until both a non-zero bit is re-

ceived and the RSR has been read at

least once since the flag was set. Break

indication will not occur if the receive buff-

er is full.

M/CIP :

Match/Character in Progress. If the syn-

chronous format is selected, this flag is

the Match flag. It will be set each time the

word transferred to the receive buffer

matches the sync character. It will be re-

set each time the word transferred to the

receive buffer does not match the sync

character. If the asynchronous format is

selected, this flag represents Character

in Progress. It will be set upon a start bit

detect and cleared at the end of the word.

SS :

Sync Strip Enable. If this bit is set to a

one, data words that match the sync

character will not be loaded into the re-

ceive buffer, and no buffer full signal will

be generated.

RE :

Receiver Enable. This control bit is used

to enable or disable the receiver. If a zero

is written to this bit of the RSR, the recei-

ver will turn off immediately. All flags in-

cluding the F/S bit will be cleared. If a one

is written to this bit, normal receiver ope-

ration is enabled. The receive clock has

to be running before the receiver is en-

abled.

V000364

MK68901

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