TDA7575B

I2C bus interface

17/32

Figure 27.

Figure 28.

Timing acknowledge clock pulse

5.5

1

Ω capability setting

It is possible to drive 1

Ω load paralleling the outputs into a single channel.

In order to implement this feature, outputs are to be connected on the board as follows:

OUT1+ (PIN35 and PIN36) shorted to OUT2+ (PIN19 and PIN20)

OUT1- (PIN28 and PIN29) shorted to OUT2- (PIN26 and PIN27).

It is recommended to minimize the impedance on the board between OUT2 and the load in

order to minimize THD distortion. It is also recommended to control the maximum mismatch

PWGND pins (PIN24/PIN25 respect to PIN30/PIN31), mismatch that must not exceed a

value of 20 m

Ω.

With 1

Ω feature settled the active input is IN2 (PIN17 and PIN18), therefore IN1 pins should

be let floating.

It is possible to set the load capability acting on 1

Ω pin as follows:

1

Ω PIN (PIN15) < 1.5V: two channels mode (for a minimum load of 2Ω)

1

Ω PIN (PIN15) > 2.5V: one channel mode (for 1Ω load).

IT IS TO REMEMBER THAT 1

OHM FUNCTION IS A HARDWARE SELECTION.

Therefore it is recommended to leave 1

Ω PIN floating or shorted to GND to set the two

channels mode configuration, or to short 1

Ω PIN to V

configuration.

5.6

TDA7575B by means of the usual ST-BY and MUTE pins. In order to activate or deactivate

SCL

SDA

START

STOP

D99AU1032

SCL

1

MSB

23789

SDA

START

ACKNOWLEDGMENT

FROM RECEIVER

D99AU1033