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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MCP4725 데이터시트(PDF) 24 Page - Microchip Technology |
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MCP4725 데이터시트(HTML) 24 Page - Microchip Technology |
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24 / 42 page  MCP4725 DS22039C-page 24 © 2007 Microchip Technology Inc. TABLE 7-1: I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for T A = -40 to +85°C, VDD = +2.7V to +5.0V, VSS = 0V. Parameters Sym Min Typ Max Units Conditions Standard Mode Clock frequency fSCL 0 — 100 kHz Clock high time THIGH 4000 — — ns Clock low time TLOW 4700 — — ns SDA and SCL rise time (Note 1) TR — — 1000 ns From VIL to VIH SDA and SCL fall time (Note 1) TF — — 300 ns From VIH to VIL START condition hold time THD:STA 4000 — — ns After this period, the first clock pulse is generated. Repeated START condition setup time TSU:STA 4700 — — ns Only relevant for repeated Start condition Data hold time (Note 3) THD:DAT 0 — 3450 ns Data input setup time TSU:DAT 250 — — ns STOP condition setup time TSU:STO 4000 — — ns STOP condition hold time THD:STD 4000 — — ns Output valid from clock (Notes 2 and 3) TAA 0 — 3750 ns Bus free time TBUF 4700 — — ns Time between START and STOP conditions. Fast Mode Clock frequency TSCL 0 — 400 kHz Clock high time THIGH 600 — — ns Clock low time TLOW 1300 — — ns SDA and SCL rise time (Note 1) TR 20 + 0.1Cb — 300 ns From VIL to VIH SDA and SCL fall time (Note 1) TF 20 + 0.1Cb — 300 ns From VIH to VIL START condition hold time THD:STA 600 — — ns After this period, the first clock pulse is generated Repeated START condition setup time TSU:STA 600 — — ns Only relevant for repeated Start condition Data hold time (Note 4) THD:DAT 0 — 900 ns Data input setup time TSU:DAT 100 — — ns STOP condition setup time TSU:STO 600 — — ns STOP condition hold time THD:STD 600 — — ns Output valid from clock (Notes 2 and 3) TAA 0 — 1200 ns Bus free time TBUF 1300 — — ns Time between START and STOP conditions. Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. 4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 5: All timing parameters in high-speed modes are tested at VDD = 5V. |
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