9DB233

TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

IDT®

TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

11

9DB233

OCTOBER 20, 2016

SMBus Table: Device Control Register, READ/WRITE ADDRESS (D5/D4)

Pin #

Name

Control Function Type0

1

Default

Bit 7

SW_EN

Enables SMBus

Control of bite 1

and 0

RW

PLL Functions

controlled by

SMBus

registers

PLL

Functions

controlled by

device pins

1

Bit 6

RW

X

Bit 5

RW

X

Bit 4

RW

X

Bit 3

RW

X

Bit 2

RW

X

Bit 1

PLL BW #adjust

Selects PLL

Bandwidth

RW

Low BW

High BW

1

Bit 0

PLL Enable

Bypasses PLL for

board test

RW

PLL bypassed

(fan out mode)

PLL enabled

(ZDB mode)

1

SMBus Table: Output Enable Register

Pin #

Name

Control Function Type0

1

Default

Bit 7

RW

X

Bit 6

RW

X

Bit 5

RW

X

Bit 4

RW

X

Bit 3

RW

X

Bit 2

RW

X

Bit 1

RW

X

Bit 0

RW

X

SMBus Table: Function Select Register

Pin #

Name

Control Function Type0

1

Default

Bit 7

RW

X

Bit 6

RW

X

Bit 5

RW

X

Bit 4

RW

X

Bit 3

RW

X

Bit 2

RW

X

Bit 1

RW

X

Bit 0

RW

X

SMBus Table: Vendor & Revision ID Register

Pin #

Name

Control Function Type0

1

Default

Bit 7

RID3

R

-

-

0

Bit 6

RID2

R

-

-

0

Bit 5

RID1

R

-

-

0

Bit 4

RID0

R

-

-

1

Bit 3

VID3

R

-

-

0

Bit 2

VID2

R

-

-

0

Bit 1

VID1

R

-

-

0

Bit 0

VID0

R

-

-

1

RESERVED

-

RESERVED

-

RESERVED

-

-

RESERVED

-

RESERVED

-

-

RESERVED

-

RESERVED

-

-

RESERVED

RESERVED

-

RESERVED

-

RESERVED

-

-

RESERVED

-

RESERVED

-

Byte 0

-

-

RESERVED

-

RESERVED

-

RESERVED

-

-

RESERVED

-

-

RESERVED

-

-

-

Byte 1

-

-

-

-

-

-

-

-

Byte 2

-

-

-

-

-

-

Byte 3

-

REVISION ID

-

-

-

-

VENDOR ID

-

-

-

RESERVED

-

RESERVED

-

RESERVED