9DB833

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

3

9DB833

MAY 25, 2018

Pin Descriptions

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

SRC_DIV#

IN

Active low Input for determining SRC output frequency SRC or SRC/2.

0 = SRC/2, 1= SRC

2

VDDR

PWR

Power supply for differential input clock (receiver). This VDD should be treated

as an analog power rail and filtered appropriately. Nominally 3.3V.

3

GND

GND

Ground pin.

4

SRC_IN

IN

HCSL SRC TRUE input

5

SRC_IN#

IN

HCSL SRC COMPLEMENTARY input

6OE0#

IN

Active low input for enabling output 0.

1 = disable output, 0 = enable output.

7OE3#

IN

Active low input for enabling output 3.

1 = disable output, 0 = enable output.

8

DIF_0

OUT

HCSL true clock output.

9

DIF_0#

OUT

HCSL complementary clock output.

10

GND

GND

Ground pin.

11

VDD

PWR

Power supply, nominally 3.3V.

12

DIF_1

OUT

HCSL true clock output.

13

DIF_1#

OUT

HCSL complementary clock output.

14

OE1#

IN

Active low input for enabling output 1.

1 = disable output, 0 = enable output.

15

OE2#

IN

Active low input for enabling output 2.

1 = disable output, 0 = enable output.

16

DIF_2

OUT

HCSL true clock output.

17

DIF_2#

OUT

HCSL complementary clock output.

18

GND

GND

Ground pin.

19

VDD

PWR

Power supply, nominally 3.3V.

20

DIF_3

OUT

HCSL true clock output.

21

DIF_3#

OUT

HCSL complementary clock output.

22

BYP#_HIBW_LOBW

IN

Tri-level input to select bypass mode, Hi BW PLL, or Lo BW PLL mode

23

SMBCLK

IN

Clock pin of SMBUS circuitry

24

SMBDAT

I/O

Data pin of SMBUS circuitry