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high value capacitor and this produces a very high peak current, responsible of many

problems:

●

Spikes on the device supply voltage that cause oscillations (and thus noise) due to the

board parasitics.

●

Turn ON overcurrent causing a decrease of the efficiency and system reliability.

●

Big EMI problems.

●

Shorter freewheeling diode life.

The fall time of the current during the turn off is also critical. In fact it produces voltage

spikes (due to the parasitics elements of the board) that increase the voltage drop across

the PDMOS.

In order to minimize all these problems, a new topology of driving circuit has been used and

The basic idea is to change the current levels used to turn on and off the power switch,

according with the PDMOS status and with the gate clamp status.

This circuitry allow to turn off and on quickly the power switch and to manage the above

question related to the freewheeling diode recovery time problem.

The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than

Vgsmax. The ON/OFF control block avoids any cross conduction between the supply line

and ground.

Figure 6.

Driving circuitry