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ST7LITE3XF2 데이터시트(PDF) 136 Page - STMicroelectronics |
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ST7LITE3XF2 데이터시트(HTML) 136 Page - STMicroelectronics |
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136 / 173 page ![]() ST7LITE3xF2 136/173 OPERATING CONDITIONS (Cont’d) 13.3.1.2 Devices with tested for TA = -40 to +125°C @ VDD = 3.0 to 3.6V Notes: 1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23. 3. Data based on characterization results, not tested in production 4. Measurement made with RC calibrated at 1MHz. 5. Guaranteed by design. 6. Averaged over a 4ms period. After the LOCKED bit is s et, a period of tSTAB is required to reach ACCPLL accuracy 7. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24. Symbol Parameter Conditions Min Typ Max Unit fRC 1) Internal RC oscillator fre- quency RCCR = FF (reset value), TA=25°C, VDD= 3.3V 630 kHz RCCR=RCCR12) ,TA=25°C,VDD= 3.3V 995 1000 1005 ACCRC Accuracy of Internal RC oscillator when calibrated with RCCR=RCCR1 2)3) TA=25°C, VDD=3.0 to 3.6V -1 +1 % TA=-40 to +85°C, VDD=3.0 to 3.6V -3 +3 TA=-40 to +125°C, VDD=3.0 to 3.6V -3 +3 IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=3.3V 5003)4) µA tsu(RC) RC oscillator setup time TA=25°C,VDD=3.3V 102) µs fPLL x4 PLL input clock 1 MHz tLOCK PLL Lock time7) 2ms tSTAB PLL Stabilization time7) 4ms ACCPLL x4 PLL Accuracy fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V 0.16) % fRC = 1MHz@TA=-40 to +125°C, VDD= 3.3V 0.16) % tw(JIT) PLL jitter period fRC = 1MHz 85) kHz JITPLL PLL jitter ( ∆f CPU/fCPU)1 5) % IDD(PLL) PLL current consumption TA=25°C 4503) µA |
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