ST7LITE3XF2 datasheet(139/173 Pages) STMICROELECTRONICS

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ST7LITE3xF2

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13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to 125°C, unless otherwise specified

Notes:

1. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset.

When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU.

2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is rec-

ommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 98 on

page 154.

13.3.3 Auxiliary Voltage Detector (AVD) Thresholds,

TA = -40 to 125°C, unless otherwise specified

13.3.4 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High Threshold, TA=-40 to +85°C

High Threshold, TA=-40 to +125°C

Med. Threshold

Low Threshold

3.60

3.05

2.45

4.15

3.45

2.85

4.60

4.65

3.90

3.20

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

3.40

2.90

2.40

3.95

3.30

2.70

4.35

3.70

3.00

Vhys

LVD voltage threshold hysteresis

VIT+(LVD)-VIT-(LVD)

200

VtPOR

VDD rise time rate

1)2)

100000

µs/V

tg(VDD)

Filtered glitch delay on VDD

Not detected by the LVD

150

IDD(LVD)

LVD/AVD current consumption

220

µA

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(AVD)

1=>0 AVDF flag toggle threshold

(VDD rise)

High Threshold, TA=-40 to +85°C

High Threshold, TA=-40 to +125°C

Med. Threshold

Low Threshold

3.90

3.45

2.90

4.45

3.90

3.30

4.85

4.90

4.30

3.65

VIT-(AVD)

0=>1 AVDF flag toggle threshold

(VDD fall)

High Threshold, TA=-40 to +85°C

High Threshold, TA=-40 to +125°C

Med. Threshold

Low Threshold

3.85

3.80

3.35

2.75

4.40

3.85

3.15

4.80

4.20

3.50

Vhys

AVD voltage threshold hystere-

sis

VIT+(AVD)-VIT-(AVD)

150

∆V

IT-

Voltage drop between AVD flag

set and LVD reset activation

VDD fall

0.45

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(RC)

Internal RC Oscillator operating voltage

Refer to operating range

of VDD with TA, section

13.3.1 on page 133

2.7

5.5

VDD(x4PLL)

x4 PLL operating voltage

2.7

3.6

VDD(x8PLL)

x8 PLL operating voltage

3.3

5.5

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