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PSD211R 데이터시트(PDF) 17 Page - STMicroelectronics |
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PSD211R 데이터시트(HTML) 17 Page - STMicroelectronics |
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17 / 51 page ![]() PSD211R Family 14 Figure 6. Port B Pin Structure READ PIN READ DATA PORT B PIN MCU I/O OUT WRITE DATA CK D R DFF ENABLE MUX CSn CONTROL DIR FF D CK R WRITE DIR RESET READ DIR I N T E R N A L I N T E R N A L C S O U T D A T A B U S B U S C S 0 • • • 7 D 8 • • • D 1 5 10.0 I/O Port Functions (Cont.) 10.3 Port B (PB0-PB7) MCU I/O Mode The default configuration of Port B is MCU I/O. In this mode, every pin can be set (at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the pin. The contents of the Pin Register indicate the true state of the PSD driving the pin through the DFF or an external source driving the pin. Chip Select Output Alternatively, each bit of Port B can be configured to provide a chip-select output signal from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is not limited to chip selects only; they can be used for generic combinatorial logic as well. Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7 signals is comprised of two product terms. The control registers of Port B are located in CSIOPORT space; see Table 5. Each pin of Port B can be individually configured. The following table summarizes what the control registers (in CSIOPORT space) for Port B do: NOTE: 1. Default value is the value after reset. Default Value Register Name 0 Value 1 Value (Note 1) Port B Pin Register Sampled logic level Sampled logic level X at pin = ‘0’ at pin = ‘1’ Port B Direction Register Pin is configured Pin is configured 0 as input as output Port B Data Register Data in DFF = ‘0’ Data in DFF = ‘1’ 0 |
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