PSD834F2V datasheet(76/89 Pages) STMICROELECTRONICS

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PSD834F2V

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Table 48. Write Timing

Note: 1. Any input used to select an internal PSD function.

2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.

3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.

4. Assuming data is stable before active write signal.

5. Assuming write is active before data becomes valid.

6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

Symbol

Parameter

Conditions

-10

-15

-20

Unit

Min

Max

Min

Max

Min

Max

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 1)

910

tLXAX

Address Hold Time

(Note 1)

912

tAVWL

Address Valid to Leading

Edge of WR

(Notes 1,3)

tSLWL

CS Valid to Leading Edge of WR

(Note 3)

tDVWH

WR Data Setup Time

(Note 3)

tWHDX

WR Data Hold Time

(Note 3)

tWLWH

WR Pulse Width

(Note 3)

tWHAX1

Trailing Edge of WR to Address Invalid

(Note 3)

tWHAX2

Trailing Edge of WR to DPLD Address

Invalid

(Note 3,6)

tWHPV

Trailing Edge of WR to Port Output

Valid Using I/O Port Data Register

(Note 3)

tDVMV

Data Valid to Port Output Valid

Using Macrocell Register Preset/Clear

(Notes 3,5)

tAVPV

Address Input Valid to Address

Output Delay

(Note 2)

tWLMV

WR Valid to Port Output Valid Using

Macrocell Register Preset/Clear

(Notes 3,4)

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