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MPC852T 데이터시트(PDF) 52 Page - Freescale Semiconductor, Inc |
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MPC852T 데이터시트(HTML) 52 Page - Freescale Semiconductor, Inc |
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52 / 80 page ![]() MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 52 Freescale Semiconductor CPM Electrical Characteristics Figure 50. Ethernet Collision Timing Diagram Figure 51. Ethernet Receive Timing Diagram 135 RSTRT active delay (from TCLK3 falling edge) 10 50 ns 136 RSTRT inactive delay (from TCLK3 falling edge) 10 50 ns 137 REJECT width low 1 — CLK 138 CLKO1 low to SDACK asserted2 —20 ns 139 CLKO1 low to SDACK negated 2 —20 ns 1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1. 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. Table 22. Ethernet Timing (continued) Num Characteristic All Frequencies Unit Min Max CLSN(CTS1) 120 (Input) RCLK3 121 RxD3 (Input) 121 RENA(CD3) (Input) 125 124 123 127 126 Last Bit |
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