AD5544/AD5554

Rev. A | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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27

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25

24

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20

19

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17

16

15

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3

4

5

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11

12

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AD5544/

AD5554

TOP VIEW

(Not to Scale)

MSB

DGND

CLK

SDO

SDI

NC

NC = NO CONNECT

LDAC

CS

RS

Figure 3. AD5544/AD5554 Pin Configuration

Table 4. Pin Function Descriptions

Pin

No.

Name

Function

1

DAC A Analog Ground.

2

DAC A Current Output.

3

4

Establish voltage output for DAC A by connecting to external amplifier output.

5

MSB

6

RS

7

Positive Power Supply Input. Specified range of operation 5 V ±10%.

8

CS

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input

register when CS/LDAC returns high. Does not effect LDAC operation.

9

CLK

Clock Input. Positive edge clocks data into shift register.

10

SDI

Serial Data Input. Input data loads directly into the shift register.

11

Establish voltage output for DAC B by connecting to external amplifier output.

12

13

DAC B Current Output.

14

DAC B Analog Ground.

15

DAC C Analog Ground.

16

DAC C Current Output.

17

18

Establish voltage output for DAC C by connecting to external amplifier output.

19

NC

No Connect. Leave pin unconnected.

20

SDO

Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544

and 17 clock pulses for AD5554 after input at the SDI pin.

21

LDAC

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous

active low input. See Table 5 and Table 6 for operation.

22

AGNDF

High Current Analog Force Ground.

23

VSS

Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.

24

DGND

Digital Ground Pin.

25

Establish Voltage Output for DAC D by Connecting to External Amplifier Output.

26

27

DAC D Current Output.

28

DAC D Analog Ground.