HT46C46 datasheet(21/77 Pages) HOLTEK

21 / 77 page

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.30

June 5, 2008

Timer Register - TMR

The TMR register is an 8-bit special function register lo-

cation within the special purpose Data Memory where

the actual timer value is stored. The value in the timer

registers increases by one each time an internal clock

pulse is received or an external transition occurs on the

PA4/TMR pin. The timer will count from the initial value

loaded by the preload register to the full count value of

FFH at which point the timer overflows and an internal

interrupt signal generated. The timer value will then be

reset with the initial preload register value and continue

counting. For a maximum full range count of 00H to FFH

the preload register must first be cleared to 00H. It

should be noted that after power-on the preload register

will be in an unknown condition. Note that if the

Timer/Event Counter is not running and data is written to

its preload register, this data will be immediately written

into the actual counter. However, if the counter is en-

abled and counting, any new data written into the

preload register during this period will remain in the

preload register and will only be written into the actual

counter the next time an overflow occurs.

Timer Control Register - TMRC

The flexible features of the Holtek microcontroller

Timer/Event Counters enable them to operate in three

different modes, the options of which are determined by

the contents of the Timer Control Register TMRC. To-

gether with the TMR register, these two registers control

the full operation of the Timer/Event Counters. Before

the timer can be used, it is essential that the TMRC reg-

ister is fully programmed with the right data to ensure its

correct operation, a process that is normally carried out

during program initialisation.

To choose which of the three modes the timer is to oper-

ate in, the timer mode, the event counting mode or the

pulse width measurement mode, bits TM0 and TM1

must be set to the required logic levels. The timer-on bit

TON or bit 4 of the TMRC register provides the basic

on/off control of the timer, setting the bit high allows the

counter to run, clearing the bit stops the counter. Bits

0~2 of the TMRC register determine the division ratio of

the input clock prescaler. The prescaler bit settings have

no effect if an external clock source is used. If the timer

is in the event count or pulse width measurement mode

the active transition edge level type is selected by the

logic level of the TE or bit 3 of the TMRC register.

T M R C R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7

E v e n t C o u n t e r A c t i v e E d g e S e l e c t

1 : c o u n t o n f a l l i n g e d g e

0 : c o u n t o n r i s i n g e d g e

T E

T O N

T M 0

T M 1

T i m e r P r e s c a l e r R a t e S e l e c t

b 0

P S C 2 P S C 1 P S C 0

P S C 1

P S C 2

P S C 0

T i m e r R a t e

1 : 1

1 : 2

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

T i m e r / E v e n t C o u n t e r C o u n t i n g E n a b l e

1 : e n a b l e

0 : d i s a b l e

O p e r a t i n g M o d e S e l e c t

T M 1

T M 0

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

P u l s e W i d t h M e a s u r e m e n t A c t i v e E d g e S e l e c t

1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e

0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

Timer/Event Counter Control Register

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