SBPH400-3 datasheet(29/43 Pages) STMICROELECTRONICS

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SBPH400-3

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On Power on, the Reset# pin should be held low for 2ms to allow supplies to settle. To reset

the device when VDD is already present, the Reset# pin should be held low until a minimum of

100ns after the external oscillator (if used) is started and operating within specification. The

SBPH400 will wait for approximately 500

µsec to allow its internal clocking circuitry to stabilize.

At the end of the nominal 500

µsec period, the SBPH400 becomes fully operational. Prior to

the SBPH400 becoming fully operational, all outputs on the PHY/Link interface are held in high

impedance, as are the TpBias and TPA and TPB pins for all three ports. When the SBPH400

becomes fully operational, it senses the ISO, PC[0:2], CMC, LACT and PDISABLE. If ISO = 0,

then all outputs on the PHY/Link interface are taken to zero, and the SBPH400 will also then

respond to LPS if this pin is active (see 2.9.2).

2.9.2 PHY/Link Interface start-up

The PHY/Link interface is controlled by the link device via the LPS signal. In order to indicate

to the SBPH400 that the link interface is active, LPS should either be held to a logic 1 (possibly

by connecting to the V

DD supplying the link layer device) or be connected to a pulsed output

which meets the specification shown in Figure 2.15 and Table 2.20. If neither of these is true

after power reset (see above), then no signal is considered to be received on LPS, the link

interface continues to be disabled, and the SBPH400 operates as a PHY repeater.

Figure 2.15

LPS timing (isolated interface)

When LPS is asserted, the PHY/Link interface starts as illustrated in Figure 2.16

Table 2.20

LPS timings

Symbol

Parameter

Unit

Min

Typ

Max

TLPSL

LPS low time (isolated interface)

1000

TLPSH

LPS high time (Isolated interface)

1000

TLPSH

TLPSL

LPS

(isolated)

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