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DM9010 데이터시트(PDF) 40 Page - List of Unclassifed Manufacturers

부품명 DM9010
상세설명  Single Chip Ethernet Controller with General Processor Interface
PDF  61 Pages
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DM9010 데이터시트(HTML) 40 Page - List of Unclassifed Manufacturers

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DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
40
Version: DM9010-DS-P03
Apr. 28, 2005
18.14
LP_EN
1, RW
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
18.13
HBE
1,RW
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9010 is configured for full duplex operation, this
bit will be ignored (the collision/heartbeat function is invalid in
full duplex mode)
18.12
SQUELCH
1, RW
Squelch Enable
1 = Normal squelch
0 = Low squelch
18.11
JABEN
1, RW
Jabber Enable
Enables or disables the Jabber function when the DM9010 is in
10BASE-T full duplex or 10BASE-T transceiver Loopback
mode
1 = Jabber function enabled
0 = Jabber function disabled
18.10
Reserved
0, RW
Reserved
Force to 0, in application.
18.9-18.
1
Reserved
0, RO
Reserved
Read as 0, ignore on write
18.0
POLR
0, RO
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable
polarity is reversed. This bit is automatically set and cleared by
10BASE-T module
8.11 Power Down Control Register (PWDOR) - 19
Bit
Bit Name
Default
Description
19.15-19.
9
Reserved
0, RO
Reserved
Read as 0, ignore on write
19.8
PD10DRV
0, RW
Vendor power down control test
19.7
PD100DL
0, RW
Vendor power down control test
19.6
PDchip
0, RW
Vendor power down control test
19.5
PDcom
0, RW
Vendor power down control test
19.4
PDaeq
0, RW
Vendor power down control test
19.3
PDdrv
0, RW
Vendor power down control test
19.2
PDedi
0, RW
Vendor power down control test
19.1
PDedo
0, RW
Vendor power down control test
19.0
PD10
0, RW
Vendor power down control test
* when selected, the power down value is control by Register 20.0



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